OneNAND TCM Tightly-coupled memory

OneNAND

The OneNAND is a highly reliable embedded memory targeted for both consumer electronic, and next generation mobile phone market. With accumulated NAND flash technologies over the last decade, the company designs an ideal single memory chip based on NAND architecture integrating SRAM buffers and logic interface. The OneNAND takes both advantages from high-speed data read function of NOR flash and the advanced data storage function of NAND flash.

Application Requires	NAND	OneNAND	NOR
Fast Random Read			o
Fast Sequential Read	o	o	o
Fast Write/Program	o	o
Multi Block Erase		o (Max 64 blocks)	o
Erase Suspend/Resume		o	o
Copyback	o (EDC)	o (ECC)
Lock/Unlock/Lock-Tight		o	o
ECC	External (Hardware/Software)	Internal	X
Scalablity	o	o

http://www.linux-mtd.infradead.org/doc/onenand.html

Tightly-coupled memory

The purpose of the Tightly-Coupled Memory (TCM) is to provide low-latency memory that the processor can use without the unpredictability that is a feature of caches.

You can use TCM to hold critical routines, such as interrupt handling routines or real-time tasks where the indeterminacy(불확정성) of a cache is highly undesirable. In addition you can use it to hold scratch pad data, data types whose locality properties are not well suited to caching, and critical data structures such as interrupt stacks.

The size of each TCM can be selected independently from a minimum of 4KB to a maximum of 256KB, in powers of 2. You can configure the TCM in several ways:

-one TCM on the instruction side and one on the data side

-one TCM on the either the instruction side or the data side only

-no TCM.

The TCM Status Register in CP15 c0 identifies the TCM options and TCM sizes that have been implemented, see c0, TCM Status Register.

The Data TCM is implemented in parallel with the data cache and the Instruction TCM is implemented in parallel with the instruction cache. Each TCM has a single movable base address, specified in CP15 register c9, (see c9, Data TCM Region Register and c9, Instruction TCM Region Register).

The size of each TCM can be different to the size of a cache way, but forms a single contiguous area of memory. The entire level one memory system is shown in Figure 7.1.

You can disable each TCM to avoid an access being made to it. This gives a reduction in the power consumption. You can disable each TCM independently from the enabling of the associated cache, as determined by CP15 register c9.

Disabling the TCM invalidates the base address, so there is no unexpected hit behavior for the TCM.

The TCM region overrides memory type attributes of the MPU and all addresses within the TCM space are treated as Normal, Non-Shared memory.

www.arm.com

Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt

Vector table. ARM internal ROM boot options include—NAND (with SPI EEPROM Boot option), SPI,

UART and MMC/SD. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled

memory interface that provides for separate instruction and data bus connections. Since the ARM TCM

does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both

data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the

RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA

support for direct accesses to the ARM internal memory from a non-ARM master. Because of the

time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are

treated as DMA transfers.

Instruction and Data accesses are differentiated via accessing different memory map regions, with the

instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the

instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,

as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB

each, which allows simultaneous instruction and data accesses to be accomplished if the code and data

are in separate banks.

www.ti.com